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Service composition partitioning method based on process partitioning technology
LIU Huijian, LIU Junsong, WANG Jiawei, XUE Gang
Journal of Computer Applications    2020, 40 (3): 799-805.   DOI: 10.11772/j.issn.1001-9081.2019071290
Abstract329)      PDF (843KB)(279)       Save
In order to solve the bottleneck existed in the central controller of centralized service composition, a method of constructing decentralized service composition based on process partitioning was proposed. Firstly, the business process was modeled by the type directed graph. Then, a grouping algorithm was proposed based on the graph transformation method, and the process model was partitioned according to the grouping algorithm. Finally, the decentralized service composition was constructed according to the partitioning results. Test results show that compared with single thread algorithm, the grouping algorithm has the time-consuming for model 1 reduced by 21.4%, and the decentralized service composition constructed has lower response time and higher throughput. The experimental results show that the proposed method can effectively partition the business processes in the service composition, and the constructed decentralized service composition can improve the service performance.
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Parallel test scheduling optimization method for three-dimensional chip with multi-core and multi-layer
CHEN Tian, WANG Jiawei, AN Xin, REN Fuji
Journal of Computer Applications    2018, 38 (6): 1795-1800.   DOI: 10.11772/j.issn.1001-9081.2017123002
Abstract443)      PDF (1090KB)(307)       Save
In order to solve the problem of high cost of chip testing in the process of Three-Dimensional (3D) chip manufacturing, a new scheduling method based on Time Division Multiplexing (TDM) was proposed to optimize the testing resources between layers, layer and core cooperatively. Firstly, the shift registers were arranged on each layer of 3D chip, and the testing frequency was divided properly between the layers and cores of the same layer under the control of shift register group on input data, so that the cores in different locations could be tested in parallel. Secondly, greedy algorithm was used to optimize the allocation of registers for reducing the free test cycles of core parallel test. Finally, Discrete Binary Particle Swarm Optimization (DBPSO) algorithm was used to find out the best 3D stack layout, so that the transmission potential of the Through Silicon Via (TSV) could be adequately used to improve the parallel testing efficiency and reduce the testing time. The experimental results show that, under the power constraints, the utilization rate of the optimized whole Test Access Mechanism (TAM) is increased by an average of 16.28%, and the testing time of the optimized 3D stack is reduced by an average of 13.98%. The proposed method can decrease the time and reduce the cost of testing.
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